Forbes

The ISA Wars Have Ended And The Heterogeneous CPU Era Has Arrived

Discussions about CPUs often frame one instruction set architecture (ISA) against another—x86 vs. Arm, Arm vs. RISC-V, and so on. However, it’s common to use multiple CPU architectures in a single ...
Business Wire

Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition

TOKYO--(BUSINESS WIRE)--Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, announced today that it has designed and tested a 32-bit CPU core based on ...
Semiconductor Engineering

Dual Instruction-Set Architecture, Supporting A TTA And RISC-V Instruction Set Via a Lightweight Microcode Hardware Unit

A technical paper titled “Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode” was published by researchers at Tampere University. “Transport triggered architectures ...
Geeky Gadgets

Ubitium’s Universal RISC-V Processor: A New Era in AI Integration

The universal RISC-V processor developed by Ubitium combines the functionalities of CPU, GPU, DSP, and FPGA into a single, unified chip. This integration is achieved through a workload-agnostic ...
Business Wire

Renesas Introduces Industry’s First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core

TOKYO--(BUSINESS WIRE)--Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced the industry’s first general-purpose 32-bit RISC-V-based ...
TweakTown

SiFive intros new SiFive Performance P870-D, a new RISC-V processor with up to 256 cores

The new SiFive Performance P870-D continues the journey for the company from its regular P870, which had a six-wide out-of-order core with an RVA23 profile of the RISC-V instruction set architecture ...
Hackaday

Checking In On The ISA Wars And Its Impact On CPU Architectures

An Instruction Set Architecture (ISA) defines the software interface through which for example a central processor unit (CPU) is controlled. Unlike early computer systems which didn’t define a ...
Nasdaq

ECARX Holdings Inc. Introduces EXP01 Processor at RISC-V Summit Europe 2025, Advancing Intelligent Mobility Solutions

ECARX launched its RISC-V-based EXP01 processor and outlined its automotive-grade MCU roadmap at the RISC-V Summit Europe 2025. ECARX Holdings Inc., a global mobility tech provider, introduced its ...
Semiconductor Engineering

Increasing Design Flexibility With RISC-V-Based Processor IP

The semiconductor industry increasingly needs more flexible and scalable processor architectures, driving the growing adoption of RISC-V. Originally developed at the University of California, Berkeley ...
EDN

RISC-V’s embedded foray with a 32-bit MCU development

One of the largest vendors of embedded processors has independently developed a CPU core for the 32-bit general-purpose RISC-V market; it can be used as the main CPU or on-chip subsystem and can even ...
TechSpot

DeepComputing announces new tablet based on the RISC-V architecture

In context: After introducing the world's first RISC-V laptop, DeepComputing is now launching what is expected to be the first fully-fledged mobile platform based on the open ISA. The company is ...
Digi Times

Arm beats Intel and AMD in DPUs; can RISC-V reshape competition?

Data centers are often seen as battlegrounds among the three major CPU architectures (x86, Arm, RISC-V) and GPUs from Nvidia, AMD, and specialized ASIC vendors. The Arm architecture has already ...