In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize ...

A massive gate structure is being welded in place out in the field. The welders work efficiently to align secure and ...

FARGO — Progress on the metro flood-control project took another big step forward with selection of the contractor that will build the largest of three gated control structures to regulate the flows ...

The IC industry is headed toward a new era of scaling–and uncertainty–as chip makers race to develop the key building blocks for the next-generation transistor: high-k dielectrics and metal gates.

R&D center IMEC has extended its industrial affiliation program (IIAP) on high-k dielectrics for sub-65nm devices to provide solutions for the implementation of metal gate stacks in planar scaled CMOS ...